This allows the processor to keep working closer to its true speed. The cache controller constructed into the processor is also answerable for watching the reminiscence bus when various processors, generally known as busmasters, are in control of the system. This means of watching the bus is known as bus snooping. If a busmaster system writes to an space of reminiscence that also is stored within the processor cache presently, the cache contents and reminiscence now not agree. The cache controller then marks this knowledge as invalid and reloads the cache in the course of the next memory entry, preserving the integrity of the system. If you decide on marking 4 areas within the book, you’ve basically constructed a four-way set associative cache.